Horizontal interdigitated capacitor structure with vias

ABSTRACT

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor disposed on the substrate, the capacitor having an anode component that includes a plurality of first conductive features and a cathode component that includes a plurality of second conductive features. The first conductive features and the second conductive features each include two metal lines extending along the first axis. At least one metal via extending along a third axis that is perpendicular to the surface of the substrate and interconnecting the two metal lines. The first conductive features are interdigitated with the second conductive features along both the second axis and the third axis.

CROSS-REFERENCE

The present disclosure is related to the following commonly-assignedU.S. patent applications, the entire disclosures of which areincorporated herein by reference: U.S. Ser. No. 13/158,044 filed Jun.10, 2011 by inventors Hsiu-Ying Cho for “A VERTICAL INTERDIGITATEDSEMICONDUCTOR CAPACITOR”; U.S. Ser. No. 13/212,982 filed Aug. 20, 2011by inventor Hsiu-Ying Cho for “VERTICALLY ORIENTED SEMICONDUCTOR DEVICEAND SHIELDING STRUCTURE THEREOF”; U.S. Ser. No. 13/280,786 filed Oct.25, 2011 by inventor Hsiu-Ying Cho for “STRUCTURE AND METHOD FOR AHIGH-K TRANSFORMER WITH CAPACITIVE COUPLING”; and U.S. Ser. No.13/272,866 filed Oct. 13, 2011 by inventor Hsiu-Ying Cho for “VERTICALLYORIENTED SEMICONDUCTOR DEVICE AND SHIELDING STRUCTURE THEREOF”.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs where each generation has smaller and more complexcircuits than the previous generation. However, these advances haveincreased the complexity of processing and manufacturing ICs and, forthese advances to be realized, similar developments in IC processing andmanufacturing are needed. In the course of integrated circuit evolution,functional density (i.e., the number of interconnected devices per chiparea) has generally increased while geometry size (i.e., the smallestcomponent or line that can be created using a fabrication process) hasdecreased.

Various active or passive electronic components can be formed on asemiconductor IC. For example, a semiconductor capacitor may be formedas a passive electronic component. Traditionally, a semiconductorcapacitor may have a metal-on-metal (MOM) structure. As device sizescontinue to decrease, the MOM structure for traditional semiconductorcapacitors may encounter problems such as excessive area consumption,low capacitance density, and/or high fabrication costs.

Therefore, while existing semiconductor capacitor devices have beengenerally adequate for their intended purposes, they have not beenentirely satisfactory in every aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a flowchart illustrating a method of fabricating asemiconductor device according to various aspects of the presentdisclosure.

FIGS. 2-3 are diagrammatic fragmentary cross-sectional side views of asemiconductor device at different stages of fabrication.

FIG. 4 is a perspective fragmentary view of a semiconductor capacitor inone embodiment.

FIG. 5 is a sectional view of the semiconductor capacitor of FIG. 4.

FIG. 6 is a sectional view of a portion of the semiconductor capacitorof FIG. 4.

FIG. 7 is a sectional view of a portion of the semiconductor capacitorof FIG. 4 in one embodiment.

FIG. 8 is a sectional view of a portion of the semiconductor capacitorof FIG. 4 in another embodiment.

FIG. 9 is a perspective view of a semiconductor capacitor in anotherembodiment.

FIG. 10 is a perspective view of a semiconductor device having acapacitor and a shield structure in one embodiment.

FIG. 11 is a perspective view of the shield structure in thesemiconductor device of FIG. 10 according to one embodiment.

FIG. 12 is a diagrammatic top view of the shield structure in thesemiconductor device of FIG. 10 according to one embodiment.

FIG. 13 is a perspective fragmentary view of a semiconductor capacitorin another embodiment.

FIG. 14 is a perspective view of a semiconductor capacitor in anotherembodiment.

FIG. 15 is a perspective view of a semiconductor device having acapacitor and a shield structure in another embodiment.

FIG. 16 is a perspective view of the shield structure in thesemiconductor device of FIG. 15 according to one embodiment.

FIG. 17 is a perspective fragmentary view of a semiconductor capacitorin another embodiment.

FIG. 18 is a perspective fragmentary view of a semiconductor capacitorin another embodiment.

FIG. 19 is a perspective view of a semiconductor device having acapacitor and a shield structure in another embodiment.

FIG. 20 is a perspective view of the shield structure in thesemiconductor device of FIG. 19 according to one embodiment.

DETAILED DESCRIPTION

It is understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of variousembodiments. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments in which the firstand second features are formed in direct contact, and may also includeembodiments in which additional features may be formed between the firstand second features, such that the first and second features may not bein direct contact. In addition, the present disclosure may repeatreference numerals and/or letters in the various examples. Thisrepetition is for the purpose of simplicity and clarity and does not initself dictate a relationship between the various embodiments and/orconfigurations discussed.

Illustrated in FIG. 1 is a flowchart of a method 20 for fabricating asemiconductor device that includes a capacitor structure. FIGS. 2 and 3are diagrammatic fragmentary cross-sectional side views of asemiconductor device 30 fabricated according to the various aspects ofthe present disclosure. The semiconductor device 30 and the method 20making the same are collectively described with references to FIGS. 1through 3.

The semiconductor device 30 may include an integrated circuit (IC) chip,system on chip (SoC), or portion thereof, that may include variouspassive and active microelectronic devices such as resistors,capacitors, inductors, diodes, metal-oxide semiconductor field effecttransistors (MOSFET), complementary metal-oxide semiconductor (CMOS)transistors, bipolar junction transistors (BJT), laterally diffused MOS(LDMOS) transistors, high power MOS transistors, or other types oftransistors. It is understood that the Figures discussed herein havebeen simplified for a better understanding of the inventive concepts ofthe present disclosure. Accordingly, it should be noted that additionalprocesses may be provided before, during, and after the method 20 ofFIG. 1, and that some other processes may only be briefly describedherein.

Referring to FIGS. 1 and 2, the method 20 begins with block 22 in whicha substrate 32 is provided. In one embodiment, the substrate 32 is asilicon substrate doped with either a P-type dopant such as boron, ordoped with an N-type dopant such as arsenic or phosphorous. Thesubstrate 32 may be made of some other suitable elementarysemiconductor, such as diamond or germanium; a suitable compoundsemiconductor, such as silicon carbide, indium arsenide, or indiumphosphide; or a suitable alloy semiconductor, such as silicon germaniumcarbide, gallium arsenic phosphide, or gallium indium phosphide.Further, the substrate 32 could include an epitaxial layer (epi layer),may be strained for performance enhancement, and may include asilicon-on-insulator (SOI) structure.

Although not specifically shown for the sake of simplicity, a pluralityof electronic components may be formed in the substrate 32. For example,source and drain regions of FET transistor devices may be formed in thesubstrate. The source and drain regions may be formed by one or more ionimplantation or diffusion processes. As another example, isolationstructures such as shallow trench isolation (STI) structures or deeptrench isolation (DTI) structures may be formed in the substrate toprovide isolation for the various electronic components. These isolationstructures may be formed by etching recesses (or trenches) in thesubstrate 32 and thereafter filling the recesses with a dielectricmaterial, such as silicon oxide, silicon nitride, silicon oxy-nitride,fluoride-doped silicate (FSG), and/or a low-k dielectric material knownin the art.

The substrate 32 has an upper surface 34. The surface 34 is atwo-dimensional plane that is defined by an X-axis and a Y-axis, wherethe X-axis and Y-axis are perpendicular, or orthogonal, to each other.The X-axis and the Y-axis may also be referred to as an X-direction anda Y-direction, respectively.

Referring to FIGS. 1 and 3, the method 20 begins with block 24 in whichan interconnect structure 36 is formed over the upper surface 34 of thesubstrate 32. In other words, the interconnect structure 36 is disposedover the surface 34 in a Z-axis, or a Z-direction that is perpendicularto the surface 34. The interconnect structure 36 includes a plurality ofpatterned dielectric layers and interconnected conductive layers. Theseinterconnected conductive layers provide interconnections (e.g., wiring)between circuitries, inputs/outputs, and various doped features formedin the substrate 32. In more detail, the interconnect structure 36 mayinclude a plurality of interconnect layers, also referred to as metallayers (e.g., M1, M2, M3, etc). Each of the interconnect layers includesa plurality of interconnect features, also referred to as metal lines.The metal lines may be aluminum interconnect lines or copperinterconnect lines, and may include conductive materials such asaluminum, copper, aluminum alloy, copper alloy, aluminum/silicon/copperalloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten,polysilicon, metal silicide, or combinations thereof. The metal linesmay be formed by a process including physical vapor deposition (PVD),chemical vapor deposition (CVD), sputtering, plating, or combinationsthereof.

The interconnect structure 36 includes an interlayer dielectric (ILD)layer that provides isolation between the first metal layer and thesubstrate and include inter-metal dielectric (IMD) layers that provideisolation between the metal layers. The ILD and IMD layers may include adielectric material such as an oxide material. The interconnectstructure 36 also includes a plurality of vias/contacts that provideelectrical connections between the different metal layers and/or thefeatures on the substrate. For the sake of simplicity, the metal linesin the interconnect layers, the vias/contacts interconnecting the metallines, and the dielectric material separating them are not specificallyillustrated herein.

The interconnect structure 36 is formed in a manner such that acapacitor is formed in the interconnect structure. The capacitor isformed with at least some of the conductive lines and at least some ofthe vias of the interconnect structure. The capacitor is formed to havean anode component and a cathode component. The anode component includesa plurality of first conductive features. The cathode component includesa plurality of second conductive features. The first conductive featuresand the second conductive features each include two metal linesextending along the X axis; and at least one metal via extending alongthe Z axis that is perpendicular to the surface of the substrate andinterconnecting the two metal lines. The first conductive features areinterdigitated with the second conductive features along both the Y axisand the Z axis.

According to various aspects of the present disclosure, aninterdigitated capacitor structure is formed in the interconnectstructure 36. Or stated differently, various components of theinterconnect structure 36 constitute the interdigitated capacitordisclosed herein. The capacitor structure is not shown in FIG. 3 for thesake of simplicity, but its various embodiments are illustrated in moredetail in FIGS. 4 through 20 and will be discussed in more detail by thefollowing paragraphs.

Referring now to FIG. 4, a fragmentary (partial) perspective view of anembodiment of the interdigitated capacitor structure 40 is illustratedaccording to aspects of the present disclosure. The capacitor structure40 includes an anode component 42 and a cathode component 44. The anodecomponent 42 and the cathode component 44 respectively serve as anodeand cathode terminals of the capacitor structure 40, so that anelectrical voltage can be applied through the anode and cathodeterminals. Stated differently, when the capacitor structure 40 is inoperation (functioning as a capacitor), one voltage will be appliedthroughout the anode component 42, while a different voltage will beapplied throughout the cathode component 44. The anode and cathodecomponents 42 and 44 may be considered opposite electrodes or may besaid to have different polarities. It is also understood that therelative configuration of the anode and cathode components 42 and 44 isnot critical. For example, the anode and cathode components 42 and 44may be rotated, flipped, or switched in other embodiments.

It is also understood that the dielectric material of the interconnectstructure 36 serves as the dielectric between the anode and cathodeelectrodes of the capacitor structure 40. In FIG. 4, the dielectricmaterial separates and electrically isolates the various parts of theanode component 42 from the various parts of the cathode component 44.Depending on the need and function to be performed by the capacitorstructure 40, the dielectric material of the interconnect structure 36can be carefully chosen so as to effect the desired capacitance. Forexample, the capacitance for a parallel plate capacitor can becalculated with the following equation:

$C = {ɛ_{r}ɛ_{0}\frac{A}{d}}$where C is the capacitance; A is the area of overlap of the two plates;∈_(r) is the dielectric constant of the material between the plates; ∈₀is the electric constant (∈₀≈8.854×10-12 F m⁻¹); and d is the separationbetween the plates. As such, if a high capacitance capacitor is desired,the dielectric material of the interconnect structure can be chosen tohave a high dielectric constant.

The anode component 42 and the cathode component 44 each include aplurality of (or arrays of) conductive features (or conductive stacks).Particularly, the anode component 42 includes a plurality of firstconductive features 42 a. The cathode component 44 includes a pluralityof second conductive features 44 a. According to various aspects of thepresent disclosure, these conductive stacks 42 a and 44 a each includetwo metal lines extending along the first axis; and at least one metalvia extending along the Z axis and interconnecting the two metal lines.The first conductive features 42 a are interdigitated with the secondconductive features 44 a along both the Y axis and the Z axis.

The capacitor structure 40 is further described with reference to FIGS.5 through 8. FIG. 5 is a sectional view of the capacitor structure 40cut from the virtual line AA′. Specifically, the sectional view in FIG.5 is taken from the virtual line AA′ in FIG. 4. The capacitor 40includes a plurality of first conductive features 42 a and a pluralityof second conductive features 44 a configured as an array in the planedefined by the Y axis and the Z axis. The first conductive features 42 aare interdigitated with the second conductive features 44 a along the Yaxis and the Z axis. State differently, the array includes a firstsubset of the first conductive features 42 a and the second conductivefeatures 44 a aligned along the Y axis. The first conductive features 42a in the first subset are interdigitated with the second conductivefeatures 44 a in the first subset along the Y axis. The array furtherincludes a second subset of the first conductive features 42 a and thesecond conductive features 44 a aligned along the Z axis. The firstconductive features 42 a in the second subset are interdigitated withthe second conductive features 44 a in the second subset along the Zaxis.

Each of the first conductive features 42 a and the second conductivefeatures 44 a in the capacitor 40 is further illustrated with referenceto FIGS. 6 and 8. FIG. 6 is a sectional view of a conductive feature 50when viewed along the X axis. FIG. 7 is a sectional view of theconductive feature 50 when viewed along the Y axis. FIG. 8 is asectional view of the conductive feature 50 when viewed along the Yaxis. The conductive feature 50 is one of the first conductive features42 a and the second conductive features 44 a constructed according toaspects of the present disclosure in various embodiments.

In one embodiment with reference to FIGS. 6 and 7, the conductivefeature 50 includes a first metal line 52, a second metal line 54, andone or more via features connecting the first and second metal lines 52and 54. The first and second metal lines 52 and 54 belong to respectivemetal layers. For example, the first metal line 52 belongs to a metallayer M_(n) and the second metal line 54 belongs to another metal layerM_(n+1) overlying the metal layer M_(n). The first and second metallines are oriented along the X axis. Each of the first and second metallines 52 and 54 includes a length defined along the X direction and awidth defined along the Y direction. The length is substantially greaterthan the width. In the present embodiment, the conductive feature 50includes a plurality of via features 56 configured to connect the firstand second conductive features 52 and 54 along the Z direction. The viafeatures 56 each include a first dimension in the X direction and asecond dimension in the Y direction. The first dimension issubstantially equal to the second dimension.

In another embodiment with reference to FIGS. 6 and 8, the conductivefeature 50 includes a first metal line 52, a second metal line 54, andone feature connecting the first and second metal lines 52 and 54. Thefirst and second metal lines 52 and 54 belong to respective metallayers, such as M_(n) and M_(n+1), respectively. The first and secondmetal lines are oriented along the X axis. Each of the first and secondmetal lines 52 and 54 includes a length defined along the X directionand a width defined along the Y direction. The length is substantiallygreater than the width. In the present embodiment, the conductivefeature 50 includes a via feature 56 configured to connect the first andsecond conductive features 52 and 54 along the Z direction. The viafeature 56 includes a first dimension in the X direction and a seconddimension in the Y direction. The first dimension is substantiallygreater than the second dimension. Therefore, the via feature 56, inthis embodiment, is also referred to as elongated via feature or viabar.

Referring now to FIG. 9, a fragmentary perspective view of aninterdigitated capacitor structure 60 is illustrated according toaspects of the present disclosure in another embodiment. The capacitorstructure 40 includes an anode component 42 and a cathode component 44.The anode component 42 and the cathode component 44 respectively serveas anode and cathode terminals of the capacitor structure 60, so that anelectrical voltage can be applied through the anode and cathodeterminals. The anode and cathode components 42 and 44 may be consideredopposite electrodes or may be said to have different polarities. Theanode and cathode components 42 and 44 may be rotated, flipped, orswitched in other embodiments.

In the embodiment shown in FIG. 9, the anode component 42 and thecathode component 44 each include a plurality of conductive features.Particularly, the anode component 42 includes a plurality of firstconductive features 42 a. The cathode component 44 includes a pluralityof second conductive features 44 a. The first conductive features 42 aare interdigitated with the second conductive features 44 a along boththe Y axis and the Z axis. According to various aspects of the presentdisclosure, these conductive stacks 42 a and 44 a each include two metallines extending along the first axis; and at least one metal viaextending along the Z axis and interconnecting the two metal lines. Inone embodiment, at least a subset of the conductive stacks 42 a and 44 ais similar to the conductive feature 50 in FIG. 7. In anotherembodiment, at least a subset of the conductive stacks 42 a and 44 a issimilar to the conductive feature 50 in FIG. 8.

The anode component 42 also includes a side portion 62, and the cathodecomponent 44 also includes a side portion 64. The side portions 62 and64 each include a plurality of metal lines interconnected vertically (inthe Z-direction) by vias, where the metal lines extend in the Ydirection. The metal lines in the side portions 62 and 64 belong torespective metal layers. The side portions 62 and 64 are formed in aplurality of metal layers. As one example illustrated in FIG. 9, theside portions 62 and 64 are formed in six consecutive metal layers. Inone embodiment, the side portions 62 and 64 each span in a plane definedby the Y axis and the Z axis. Furthermore, the side portions 62 and 64are defined in an area aligned with the array of the conductive features42 a and 44 a when viewed in the X direction.

The conductive features 42 a extend in the X direction and connect tothe side portion 62. The conductive features 44 a extend in the Xdirection and connect to the side portion 64. It is understood that inother embodiments, the anode component 42 may have the side portion 62positioned at the right side and connected to the conductive features 42a, and the cathode component 42 may have the side portion 64 positionedat the left side and connected to the conductive features 44 a. In otherembodiments, the side portions may also have alternative shapes anddesigns.

FIG. 10 is a fragmentary perspective view of a semiconductor structure70 having an interdigitated capacitor 72 and a shield structure 74surrounding the capacitor 72 constructed according to aspects of thepresent disclosure in one or more embodiments.

In one embodiment, the capacitor 72 is similar to the capacitor 60 ofFIG. 9. Particularly, the capacitor structure 72 includes an anodecomponent 42 and a cathode component 44. The anode component 42 and thecathode component 44 respectively serve as anode and cathode terminalsof the capacitor structure 72, so that an electrical voltage can beapplied through the anode and cathode terminals. The anode component 42and the cathode component 44 each include a plurality of conductivefeatures. Particularly, the anode component 42 includes a plurality offirst conductive features 42 a. The cathode component 44 includes aplurality of second conductive features 44 a. The first conductivefeatures 42 a are interdigitated with the second conductive features 44a along both the Y axis and the Z axis. In one example, the conductivefeatures 42 a and 44 a each may has a structure of the conductivefeature 50 of FIG. 6.

The semiconductor structure 70 includes the shield structure 74surrounding the capacitor 72 configured to provide a shield functionsuch that the capacitor 72 is electrically shield from the substrate andother conductive features (such as a portion of the interconnectstructure) approximate the capacitor 72. Therefore, the induced energyloss is substantially reduced and the quality factor of the capacitor 72is substantially increased. In one embodiment, the shield structure 74is electrically grounded.

The shield structure 74 is further described with reference to FIGS. 11and 12. FIG. 11 is a perspective view of the shield structure 74. FIG.12 is a top view of the shield structure 74 where the detailed structureis eliminated for simplicity. Referring to FIGS. 11 and 12, the shieldstructure 74 includes vertical features 76 and horizontal features 78configured to provide an enclosed space where the capacitor 72 ispositioned in. Particularly, the vertical feature 76 includes a firstside portion 76 a and a second side portion 76 b spaced along the Ydirection. The first side portion 76 a and the second portion 76 b spanalong the X direction and Z direction. The vertical feature 76 furtherincludes a third side portion 76 c and a fourth side portion 76 d spacedalong the X direction. The third side portion 76 c and the secondportion 76 d span along the Y direction and Z direction. The horizontalfeatures 78 includes a top portion 78 a and a bottom portion 78 b spacedalong the Z direction. The top portion 78 a and the bottom portion 78 bspan along the X direction and the Y direction. The first side portion76 a, the second side portion 76 b, the third side portion 76 c, thefourth side portion 76 d, the top portion 78 a, and the bottom sideportion 76 a are electrically connected and are configured to enclosethe capacitor 72 inside for shield effect.

The side portions 76 a and 76 b each include a plurality of metal linesinterconnected vertically (in the Z-direction) by vias, where the metallines extend in the X direction. The side portions 76 c and 76 d eachinclude a plurality of metal lines interconnected vertically (in theZ-direction) by vias, where the metal lines extend in the Y direction.The top portion 78 a and bottom portion 78 b each include a plurality ofmetal lines that extend in the X-direction or alternatively in the Ydirection. The metal lines of the top portion 78 a are metal lines inthe same metal layer, and the metal lines of the bottom portion 78 b aremetal lines in the same metal layer (but a different metal layer thanthe metal layer of the top portion 78 a). In other embodiments, thevertical features 76 and the horizontal features 78 may also havealternative shapes and designs. For example, the via features in theside portions 76 a, 76 b, 76 c and 76 d may be designed have equaldimensions in the X and Y directions. Alternatively, those via featuresmay be designed to have an elongated shape in a top view, or via bar.For example, the via features in the first and second side portions 76 aand 76 b includes a first dimension along the X direction and a seconddimension along the Y direction, where the first dimension issubstantially greater than the second dimension. In another example, thevia features in the third and fourth side portions 76 c and 76 dincludes a first dimension along the Y direction and a second dimensionalong the X direction, where the first dimension is substantiallygreater than the second dimension.

FIG. 13 is a fragmentary perspective view of a capacitor structure 80 inanother embodiment. The capacitor structure 80 is similar to thecapacitor structure 40 in FIG. 4. The capacitor structure 40 includes ananode component 42 and a cathode component 44. The anode component 42and the cathode component 44 each include a plurality of conductivefeatures. Particularly, the anode component 42 includes a plurality offirst conductive features 42 a. The cathode component 44 includes aplurality of second conductive features 44 a. According to variousaspects of the present disclosure, these conductive features 42 a and 44a each include two metal lines extending along the X axis; and one metalvia 82 extending along the Z axis and interconnecting the two metallines. The via features 82 are designed to have an elongated shape in atop view. The first conductive features 42 a are interdigitated with thesecond conductive features 44 a along both the Y axis and the Z axis.

FIG. 14 is a fragmentary perspective view of a capacitor structure 84 inanother embodiment. The capacitor structure 84 is similar to thecapacitor structure 80 in FIG. 13 but further includes side portions.The anode component 42 also includes a side portion 62, and the cathodecomponent 44 also includes a side portion 64. The side portions 62 and64 each include a plurality of metal lines interconnected vertically (inthe Z-direction) by elongated vias 86, where the metal lines extend inthe Y direction. The metal lines in the side portions 62 and 64 belongto respective metal layers. The side portions 62 and 64 are formed in aplurality of metal layers. As one example illustrated in FIG. 14, theside portions 62 and 64 are formed in six consecutive metal layers. Inone embodiment, the side portions 62 and 64 each span in a plane definedby the Y axis and the Z axis. Furthermore, the side portions 62 and 64are defined in an area aligned with the array of the conductive features42 a and 44 a when viewed in the X direction. The elongated via features86 are similar to the elongated via features 82 but are oriented alongthe Y direction. Particularly, the elongated via features 86 includes afirst dimension along the Y direction and a second dimension along the Xdirection, where the first dimension is substantially greater than thesecond dimension.

FIG. 15 is a fragmentary perspective view of a semiconductor structure88 including the capacitor structure 84 and a shield structure 89surrounding the capacitor 84. The shield structure 89 is furtherillustrated in FIG. 16 in a perspective view and is similar to theshield structure 74 in FIG. 11. In an alternative embodiment, the shieldstructure 89 uses elongated via features similar to the via features 86in FIG. 14. In another embodiment, the shield structure 89 iselectrically grounded.

FIG. 17 is a fragmentary perspective view of a capacitor structure 90 inanother embodiment. The capacitor structure 90 is similar to thecapacitor structure 80 in FIG. 13. The capacitor structure 40 includesan anode component 42 and a cathode component 44. The anode component 42and the cathode component 44 each include a plurality of conductivefeatures. Particularly, the anode component 42 includes a plurality offirst conductive features 42 a. The cathode component 44 includes aplurality of second conductive features 44 a. However, these conductivefeatures 42 a and 44 a each include a plurality of metal lines extendingalong the X axis; and metal vias 82 extending along the Z axis andinterconnecting neighbor metal lines. The via features 82 are designedto have an elongated shape in a top view. The elongated via features 82includes a first dimension along the X direction and a second dimensionalong the Y direction, where the first dimension is substantiallygreater than the second dimension. Furthermore, the first conductivefeatures 42 a are interdigitated with the second conductive features 44a along the Y axis.

FIG. 18 is a fragmentary perspective view of a capacitor structure 92 inanother embodiment. The capacitor structure 92 is similar to thecapacitor structure 90 in FIG. 17 but further includes side portions.The anode component 42 also includes a side portion 62, and the cathodecomponent 44 also includes a side portion 64. The side portions 62 and64 each include a plurality of metal lines interconnected vertically (inthe Z-direction) by vias 86, where the metal lines extend in the Ydirection. In one embodiment, the via features 86 are designed with anelongated shape as well. The metal lines in the side portions 62 and 64belong to respective metal layers. The side portions 62 and 64 areformed in a plurality of metal layers. As one example illustrated inFIG. 18, the side portions 62 and 64 are formed in six consecutive metallayers. In one embodiment, the side portions 62 and 64 each span in aplane defined by the Y axis and the Z axis. Furthermore, the sideportions 62 and 64 are defined in an area aligned with the array of theconductive features 42 a and 44 a when viewed in the X direction. Theelongated via features 86 are similar to the elongated via features 82.Particularly, the elongated via features 86 includes a first dimensionalong the Y direction and a second dimension along the X direction,where the first dimension is substantially greater than the seconddimension.

FIG. 19 is a fragmentary perspective view of a semiconductor structure94 including the capacitor structure 92 (as shown in FIG. 18) and ashield structure 96 surrounding the capacitor 92. The shield structure96 is further illustrated in FIG. 20 in a perspective view and issimilar to the shield structure 74 of FIG. 11. In an alternativeembodiment, the shield structure 96 uses elongated via features similarto the via features 86 in FIG. 18. In another embodiment, the shieldstructure 96 is electrically grounded.

Although various embodiments are described, other embodiments of thecapacitor having conductive features configured in an interdigitatedmanner or the capacitor having elongated via features may be usedaccording to the present disclosure. In one example, the shieldstructure may include a subset of the side portions, the top portion andthe bottom portion. In another example, elongated vias may be used inthe conductive features of the anode and cathode components, the sideportions of the anode and cathode components, the shield structure orcombinations thereof. It is understood that additional processes may beperformed to complete the fabrication of the capacitor structure. Forexample, these additional processes may include deposition ofpassivation layers, packaging, and testing. For the sake of simplicity,these additional processes are not described herein.

A semiconductor device is disclosed according to one of the broaderforms of the present disclosure. In one embodiment, the semiconductordevice includes a substrate having a surface that is defined by a firstaxis and a second axis perpendicular to the first axis; and a capacitordisposed on the substrate, the capacitor having an anode component thatincludes a plurality of first conductive features and a cathodecomponent that includes a plurality of second conductive features. Thefirst conductive features and the second conductive features eachinclude two metal lines extending along the first axis; and at least onemetal via extending along a third axis that is perpendicular to thesurface of the substrate and interconnecting the two metal lines; andthe first conductive features are interdigitated with the secondconductive features along both the second axis and the third axis.

In one embodiment, the metal via includes a first dimension along thefirst axis and a second dimension along the second axis, the firstdimension being substantially equal the second dimension. In anotherembodiment, the metal via includes a first dimension along the firstaxis and a second dimension along the second axis, the first dimensionbeing substantially greater than the second dimension.

In another embodiment, an interconnect structure having a plurality ofinterconnect layers is disposed over the substrate, and the two metallines belong to two neighbor metal layers and are distanced from eachother along the third axis. The metal lines each have a first dimensionalong the first axis greater than a second dimension along the secondaxes.

In another embodiment, the first conductive features and the secondconductive features form a two-dimension array in a sectional view alongthe first axis; and the array contains a subset of first and secondconductive features aligned along the second axis and another subset offirst and second conductive features aligned along the third axis.

In another embodiment, the anode component further includes a first sideportion connecting with the first conductive features; the cathodecomponent further includes a second side portion connecting with thesecond conductive features; the first and second side portions each spanalong both the second axis and the third axis, and the first and secondconductive features are disposed between the first and second sideportions. In furtherance of the embodiment, the first and second sideportions each include a plurality of metal lines each belong to adifferent metal layer of an interconnect structure; and a plurality ofgroups of metal vias each group of metal vias interconnect two of theplurality of metal lines along the third axis.

In another embodiment, the semiconductor device further includes ashield structure that completely surrounds the capacitor and isconfigured to be grounded. In furtherance of this embodiment, the shieldstructure includes a bottom portion; a first side portion and a secondside portion distanced along the first axis; and a third side portionand a fourth side portion distanced along the second axis, where thecapacitor is enclosed by the top portion, the bottom portion, the firstportion, the second portion, the third portion and the fourth portion.

In various embodiments, the shield structure includes a top portion,wherein the top portion and the bottom portion each include a respectiveconductive element that belongs to a metal layer of an interconnectstructure. The conductive element may includes a plurality of metallines each extending along one of the first axis and the second axis.

In another embodiment, each of first, second, third and fourth sideportions includes a plurality of metal lines interconnected along thethird axis by a plurality of metal vias, and wherein the metal lineseach extend along the second axis.

The present disclosure also provides another embodiment of asemiconductor device. The semiconductor device includes a substratehaving a surface that is defined by a first axis and a second axisperpendicular to the first axis; and a capacitor disposed on thesubstrate, the capacitor having an anode component that includes aplurality of first conductive features and a cathode component thatincludes a plurality of second conductive features. The first conductivefeatures are interdigitated with the second conductive features alongthe second axis. The first conductive features and the second conductivefeatures each include a plurality of metal lines extending along thefirst axis; and a plurality of metal vias each interconnecting two ofthe metal lines along a third axis perpendicular to the surface of thesubstrate. Each of the metal vias includes a first dimension along thefirst axis and a second dimension along the second axis, the firstdimension being substantially greater than the second dimension.

In one embodiment, an interconnect structure having a plurality ofinterconnect layers is disposed over the substrate, and the metal lineseach belong to a respective metal layer, and the metal lines each have afirst dimension along the first axis greater than a second dimensionalong the second axes.

In another embodiment, the anode component further includes a first sideportion connecting with the first conductive features; the cathodecomponent further includes a second side portion connecting with thesecond conductive features; the first and second side portions each spanalong both the second axis and the third axis, and the first and secondconductive features are disposed between the first and second sideportions.

In another embodiment, the semiconductor device further includes ashield structure configured to be grounded. The shield structureincludes a top portion and a bottom portion; a first side portion and asecond side portion distanced along the first axis; and a third sideportion and a fourth side portion distanced along the second axis. Thecapacitor is enclosed by the top portion, the bottom portion, the firstportion, the second portion, the third portion and the fourth portion.

In furtherance of the above embodiment, the top portion and the bottomportion each include a respective conductive element that belongs to ametal layer of an interconnect structure. Each of first, second, thirdand fourth side portions includes a second plurality of metal linesinterconnected along the third axis by a second plurality of metal vias.The second metal lines each extend along the second axis.

The present disclosure also provides another embodiment of a method offabricating a semiconductor device. The method includes providing asubstrate having a surface that is defined by a first axis and a secondaxis that is perpendicular to the first axis; and forming aninterconnect structure over the surface of the substrate, theinterconnect structure having a layers of conductive lines and a levelsof conductive vias interconnecting the layers of conductive lines. Theforming the interconnect structure includes forming a capacitor with asubset of the conductive lines and a subset of the conductive vias, thecapacitor having an anode component that includes a plurality of firstconductive features and a first side portion connecting the firstconductive features and a cathode component that includes a plurality ofsecond conductive features and a second side portion connecting thesecond conductive features. The first conductive features and the secondconductive features each extend along the first axis. The firstconductive feature are formed to be interdigitated with the secondconductive features along the second axis. The first and second sideportions each span along both the second axis and a third axisperpendicular to the surface. The first and second conductive featuresare disposed between the first and second side portions.

In one embodiment of the method, the forming the capacitor furtherincludes forming a shield structure that has a top portion and a bottomportion; a first side portion and a second side portion distanced alongthe first axis; and a third side portion and a fourth side portiondistanced along the second axis. The capacitor is enclosed by the topportion, the bottom portion, the first portion, the second portion, thethird portion and the fourth portion.

In another embodiment, the forming the capacitor includes forming themetal vias each with a first dimension along the first axis and a seconddimension along the second axis, the first dimension being substantiallygreater than the second dimension.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor device, comprising: a substratehaving a surface that is defined by a first axis and a second axisperpendicular to the first axis; and a capacitor disposed on thesubstrate, the capacitor having an anode component that includes aplurality of first conductive features and a first side portionconnecting with the first conductive features and a cathode componentthat includes a plurality of second conductive features and a secondside portion connecting with the second conductive features, wherein thefirst conductive features and the second conductive features eachinclude: two metal lines extending along the first axis, and at leastone metal via extending along a third axis that is perpendicular to thesurface of the substrate and interconnecting the two metal lines; thefirst conductive features are interdigitated with the second conductivefeatures along both the second axis and the third axis; and the firstside portion and the second side portion include: two conductive linesextending along the second axis; and at least one conductive viaextending along the third axis and interconnecting the two conductivelines extending along the second axis.
 2. The semiconductor device ofclaim 1, wherein the metal via includes a first dimension along thefirst axis and a second dimension along the second axis, the firstdimension being substantially equal to the second dimension.
 3. Thesemiconductor device of claim 1, wherein the metal via includes a firstdimension along the first axis and a second dimension along the secondaxis, the first dimension being substantially greater than the seconddimension.
 4. The semiconductor device of claim 1, wherein the two metallines belong to two neighbor metal layers and are distanced from eachother along the third axis.
 5. The semiconductor device of claim 4,wherein the metal lines each have a first dimension along the first axisgreater than a second dimension along the second axis.
 6. Thesemiconductor device of claim 1, wherein: the first conductive featuresand the second conductive features form a two-dimension array in asectional view along the first axis; and the array contains a subset offirst and second conductive features aligned along the second axis andanother subset of first and second conductive features aligned along thethird axis.
 7. The semiconductor device of claim 1, wherein: the firstand second conductive features are disposed between the first and secondside portions.
 8. The semiconductor device of claim 7, wherein: themetal lines of the first and second side portions belong to a differentmetal layer of an interconnect structure.
 9. The semiconductor device ofclaim 1, further comprising a shield structure that completely surroundsthe capacitor and is configured to be grounded.
 10. The semiconductordevice of claim 9, wherein the shield structure includes: a bottomportion; a first side portion and a second side portion distanced alongthe first axis; and a third side portion and a fourth side portiondistanced along the second axis, wherein the capacitor is enclosed bythe bottom portion, the first side portion, the second side portion, thethird side portion, and the fourth side portion.
 11. The semiconductordevice of claim 10, wherein the shield structure includes a top portion,wherein the top portion and the bottom portion each include a respectiveconductive element that belongs to a metal layer of an interconnectstructure.
 12. The semiconductor device of claim 11, wherein theconductive element includes a plurality of metal lines each extendingalong one of the first axis and the second axis.
 13. The semiconductordevice of claim 10, wherein each of the first, second, third and fourthside portions includes a plurality of metal lines interconnected alongthe third axis by a plurality of metal vias, and wherein the metal lineseach extend along the second axis.
 14. A method of fabricating asemiconductor device, comprising: providing a substrate having a surfacethat is defined by a first axis and a second axis that is perpendicularto the first axis; and forming an interconnect structure over thesurface of the substrate, the interconnect structure having layers ofconductive lines and levels of conductive vias interconnecting thelayers of conductive lines, wherein the forming the interconnectstructure includes: forming a capacitor with a subset of the conductivelines and a subset of the conductive vias, the capacitor having an anodecomponent that includes a plurality of first conductive features and afirst side portion connecting the first conductive features and acathode component that includes a plurality of second conductivefeatures and a second side portion connecting the second conductivefeatures, wherein: the first conductive features and the secondconductive features each extend along the first axis, the first andsecond conductive features are comprised of two of the conductive linesinterconnected by at least one of the conductive vias, the firstconductive features are formed to be interdigitated with the secondconductive features along the second axis, the first and second sideportions each span along both the second axis and a third axisperpendicular to the surface, and the first and second conductivefeatures are disposed between the first and second side portions; thefirst side portion and the second side portion include: two metal linesextending along the second axis; and at least one metal via extendingalong the third axis and interconnecting the two metal lines extendingalong the second axis.
 15. The method of claim 14, wherein the formingthe capacitor further includes forming a shield structure having: a topportion and a bottom portion; a first side portion and a second sideportion distanced along the first axis; and a third side portion and afourth side portion distanced along the second axis, wherein thecapacitor is enclosed by the top portion, the bottom portion, the firstside portion, the second side portion, the third side portion, and thefourth side portion.
 16. The method of claim 14, wherein the forming thecapacitor includes forming the conductive vias each with a firstdimension along the first axis and a second dimension along the secondaxis, the first dimension being substantially greater than the seconddimension.
 17. A semiconductor device, comprising: a substrate having asurface that is defined by a first axis and a second axis perpendicularto the first axis; an interconnect structure having a plurality ofinterconnect layers disposed over the substrate; a capacitor formed inthe interconnect structure, the capacitor having an anode component thatincludes a plurality of first conductive features and a cathodecomponent that includes a plurality of second conductive features,wherein the first conductive features and the second conductive featureseach include: two metal lines extending along the first axis, whereinthe two metal lines belong to two neighbor metal layers of theinterconnect structure and are distanced from each other along a thirdaxis that is perpendicular to the surface of the substrate, and at leastone metal via extending along the third axis and interconnecting the twometal lines; and the first and second conductive features are arrangedin a two dimensional array along both the second axis and the thirdaxis, wherein the first and second conductive features alternate alongboth the second axis and the third axis; the anode component furtherincludes a first side portion connecting with the first conductivefeatures; the cathode component further includes a second side portionconnecting with the second conductive features; the first side portionand the second side portion include: two conductive lines extendingalong the second axis; and at least one conductive via extending alongthe third axis and interconnecting the two conductive lines extendingalong the second axis.
 18. The semiconductor device of claim 17, whereinthe metal via includes a first dimension along the first axis and asecond dimension along the second axis, the first dimension beingsubstantially equal to the second dimension.
 19. The semiconductordevice of claim 17, wherein the metal via includes a first dimensionalong the first axis and a second dimension along the second axis, thefirst dimension being substantially greater than the second dimension.20. The semiconductor device of claim 17, wherein the first and secondside portions each span along both the second axis and the third axis;and the first and second conductive features are disposed between thefirst and second side portions.
 21. The semiconductor device of claim17, further comprising a shield structure configured to be grounded,wherein the shield structure includes: a top portion and a bottomportion; a first side portion and a second side portion distanced alongthe first axis; and a third side portion and a fourth side portiondistanced along the second axis, wherein the capacitor is enclosed bythe top portion, the bottom portion, the first side portion, the secondside portion, the third side portion, and the fourth side portion.